Job Description
You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits upto 10 Gbps, PCIe Gen4, USB 3.1 Gen2/Gen1, MPHY, MIPI, IOs & LVDS. You will be responsible for PLLs/DPLLs/ADC design. Knowledge of analog circuit design and intuition is important. You should be able to coordinate the circuit design teams and the logic design teams.
Mandatory Skills
High Speed Circuit design
Education Qualification
Ph.D in VLSI/Microelectronics
0-3+ years of experience in verification of analog mixed signal blocks.Hands on tool expertise
Tools:
Cadence Suite:Virtuoso, AMS tools, Verilog, VerilogA and VAMS languages
Mentor Suite: Calibre
Job Description
The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Design/verify the RTL code for the high speed SerDes related digital blocks
Mandatory Skills
Timing Closure, STA, ECOs, Synthesis, SDC
Education Qualification
BE/B.Tech in VLSI/ECE.
5+ years of experience in verification of analog mixed signal blocks.
Hands on tool expertise
Tools: cadence AMS tools and proficiency in Verilog, verilogA and VAMS languages
Job Description
You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits upto 10 Gbps, PCIe Gen4, USB 3.1 Gen2, MPHY, MIPI, IOs & LVDS.
· Working knowledge in the technology nodes of 65, 45/40, 28nm is preferred.
· Responsible for the design and implementation of the blocks related to SerDes
· Knowledge of SerDesis preferable.
· Excellent problem solving and debug skills
· Excellent verbal and written communication skills.
Education Qualification
BE/B.Tech/ M.E/M.Tech/M.S. in ECE/VLSI/Micro electronics with 5+ years of relevant experience and hands on tool expertise
Tools: cadence schematic design, simulation tools, exposure to scripting techniques.
Job Description
The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Design/verify the RTL code for the high speed SerDes related digital blocks
· Excellent verbal and written communication skills are required.
· Experience in synthesis of complex SoCs block/top level and writing timing constraints.
· Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints.
· Experience in post-layout STA closure and timing ECOs
· Worked in technology nodes 45nm and below.
Mandatory Skills
Timing Closure, STA, ECOs, Synthesis, SDC
Education Qualification
BE/B.Tech in VLSI/ECE.
3+ years of experience in verification of analog mixed signal blocks.
Hands on tool expertise
Tools: cadence AMS tools and proficiency in Verilog, verilogA and VAMS languages
Job Description
You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits up to 10 Gbps, PCIe Gen4, USB 3.1 Gen2, MPHY, MIPI, IOs & LVDS.
· Working knowledge in the technology nodes of 65, 45/40, 28nm is preferred.
· Responsible for the design and implementation of the blocks related to SerDes
· Experience of SerDes, PLL, Phase Interpolators, DC-DC convertors or ADC is preferable.
· Excellent problem solving and debug skills
· Excellent verbal and written communication skills.
Education Qualification
BE/B.Tech/ M.E/M.Tech/M.S. in ECE/VLSI/Micro electronics with 3+ years of relevant experience and hands on tool expertise
Tools: cadence schematic design, simulation tools, exposure to scripting techniques.