With ever increasing bandwidth and speed requirements for enabling future technologies, SerDes (Serializer/De-Serializer) plays a vital component for any data communication. Terminus Circuits offers a one-stop-shop solution for all SerDes designing. Terminus Circuits provides the best-in-class SerDes IP across various nodes, multiple foundries and protocols.
Deliverables:
Terminus Circuits offers unprecedented power savings and performance for customers requiring superior SerDes technology. Our SerDes IPs are available in the following nodes:.
16Gbps – TSMC 28HPC, TSMC 28HPC+
10Gbps - TSMC 65GP, TSMC 55LP
8Gbps – TSMC 65GP, TSMC 28 HPC, TSMC 28HPC+, GF 28SLP
5G/2.5Gbps – TSMC 28 HPC, TSMC 28HPC+, TSMC 65GP, TSMC 55LP, GF 28SLP
PCIe is the most common protocol in high speed serial standards to connect components in embedded systems. It leverages SerDes (Serializer/De-serializer) technology to deliver throughput and latency performance greater than what is possible with wide parallel bus technology.
Terminus Circuits offers best-in-class PHY IP for PCIe 4.0/3.0/2.0. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) and soft macro for PCIe that is PIPE4.3 compliant.
Offerings:
USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and device mode. USB 3.1 IP is targeted for integration into SoCs for media storage, and playback devices requiring faster bandwidth between PCs and portable electronic devices.
Terminus Circuits offers best-in-class SerDes IP for USB 3.1 PHY. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports USB 3.0 and USB3.1 protocols, a physical coding sublayer (PCS) and soft macro for USB that is PIPE4.2 compliant.
MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency are key criteria. It is the foundation for several upper layer protocols which manage complex data transfer functions. Each of these protocols is optimized for its particular purpose, such as data storage, data transfer, display, camera, memory sharing, and radio interface. Scalability and modularity are also important features of the MIPI M-PHY, as these features allow designers to more easily adapt to evolving system and application requirements.
The eye diagrams are given for the PRBS data pattern with the MIPI Reference-1 channel model.
Terminus Circuits SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data storage, enterprise routers, servers, industrial & test equipment, defence and aerospace etc. With seamless interoperability with available controllers it provides unique solution to customer’s system applications.
Terminus Circuits offers low power, low latency, integrated clocking and small footprint SerDes Quad PHY IP that supports one, two, four lanes per macro configuration.
Standards | Data Rate (Gbps) | Organization |
PCI Express Gen4/3/2/1 | 16/8/5/2.5 | PCI-SIG |
USB 3.1 Gen2/1 | 10/5 | USB.org |
SATA Gen 3/2/1 | 6/3/1.5 | SATA |
10GBase-KX4 | 3.125 | IEEE |
1000Base-KX | 1.25 | IEEE |
10GBase-KR / XFI | 10.3125 | IEEE |
XAUI | 3.125 | IEEE |
DisplayPort | 8.1 – 1.6 | VESA |
HSSTP | 12.5 | ARM |
EPON/GPON/XGPON | 1.25 / 2.488 / 9.95 | IEEE |
SGMII/QSGMII | 1.25/5.0 | Cisco |
Offerings: